Yuriy Kazachkov Principal Consultant yuriy.kazachkov@siemens.com	Jay Senthil Senior Staff Software Engineer jayapalan.senthil@siemens.com

The PSS®E CDC7T model simulates a pole of the 2-terminal HVDC transmission. There are significant differences between this model and generic HVDC models, such as CDC4T or CDC6T, available in the PSS®E library. The CDC4T and CDC6T models assume an instantaneous response of the dc system to disturbances coming from adjacent grids. They use the same algebra as the power flow model to update converter parameters (alpha, gamma) at each integration step. They assume that converters are capable of maintaining the steady-state control algorithm using the same set points as in power flow. There is a special algorithm of simulating blocking and by-passing HVDC that uses some threshold voltages on ac and dc sides. Because they are very sensitive to how strong interconnection to the system is, setting up these thresholds requires experience.

The CDC7T model simulates the dynamics of the dc line and converter controls. The model is generic in the sense that it does not represent any particular vendor, but the configuration of the dc circuit and algorithm used for converter control are typical of any conventional HVDC system.

DC circuit arrangement simulated by CDC7T

The dc circuit arrangement that can be simulated by the CDC7T model is shown in Figure 1. A dc line may comprise overhead lines from both rectifier and inverter sides and a cable. An overhead dc line is represented by its dc resistance and some equivalent inductance. A cable is represented by its dc resistance, equivalent inductance, and capacitance. A small resistance representing cable damping is placed in series with the cable capacitance.

The model does not include frequency-dependent sub-models for the overhead line or cable. Therefore, for the equivalent inductance and capacitance, respective values for the fundamental frequency are recommended.

Figure 1 - A DC Circuit Arrangement Simulated by the CDC7T Model

Although the dc line can be represented by a T-circuit with lumped Rdc and Ldc parameters, for the sake of flexibility the model uses resistances and inductances of overhead lines on rectifier (ROHR, LOHR) and inverter (ROHI, LOHI) sides, resistance, inductance, and capacitance of the dc cable (RDCC, LDCC, CDCC), and resistance and inductance of smoothing reactors on both sides (RRR, LRR and RRI, LRI).

By changing ICON(M+3) from 1 to 2, the model switches from the mixed overhead-cable dc line to just an overhead line. It is not recommended to make this transition by reducing the cable capacitance because of potential numeric problems. Also, if the user wishes to model a pure overhead-line, it is recommended that RDCC & LDCC be set to zero.

The model allows for the simulation of faults in the dc system. Three fictitious LR-shunts have been added to the model as shown in Figure 1. Under normal operation, parameters of these shunts have been set to very big numbers to have almost zero currents in the shunts. To simulate faults in any of three points of the dc circuit, namely, on the terminals of the overhead line from the rectifier side, on the terminals of the overhead line on the inverter side, and in the middle point of the cable, both inductance and resistance of a respective shunt should be reduced. To avoid numerical instability, the ratio of fault inductance to fault resistance (i.e., the L/R ratio) should be kept constant at 0.1.

Control Algorithm

Analysis of operation of numerous existing available HVDC projects reveals the following 3 major configurations of converter controls.

Control configuration 1:

• Rectifier in dc current control
• Inverter in gamma control

Control configuration 2:

• Rectifier in dc current control
• Inverter in dc voltage control

Control configuration 3:

• Rectifier in dc voltage control
• Inverter in dc current control

Control configuration 1 was used for the first historic HVDC projects. The second configuration is typical for modern HVDC transmissions with overhead dc lines or comparatively short cables. For HVDCs with a long cable, control configuration 3 is very likely to be implemented.

Choice of the control configuration depends on many factors, beginning with the value of a short circuit ratio at the points of interconnection of HVDC terminals with the ac system. That is why the CDC7T model has a provision for choosing the control configuration. Depending on the selected control configuration, some parameters of controls must be adjusted as recommended in the PSS®E manual.

For HVDC lines with a long HVDC cable, a special control is needed to monitor the so called compounded dc voltage (VDComp) of the cable terminal on the rectifier side to ensure that this voltage remains less than the nominal voltage.

Controls of both converters can be simulated based on the same structure, which includes 3 controllers, namely;

• DC current controller
• DC voltage controller
• Gamma controller.

The voltage dependent current limit (VDCL) control, if invoked by an ac system disturbance, will keep the dc current to the lowered limit during recovery which aids the corresponding recovery of the dc system. Only when dc voltage has recovered sufficiently will the dc current return to its original level.

The operational dc current order is calculated as a ratio of the power order and the rated dc voltage from the power flow (SETVAL and VSCHED).

This dynamic simulation model is initialized from the power flow HVDC model and uses all the pertinent information from the power flow.

The CDC7T model uses 54 parameters of the dc circuit and controls. The model uses 16 state variables (STATEs) and 24 algebraic variables (VARs); many of them can be used for plotting.

The model uses 4 integer constants (ICONs) to control the simulation and select the control configuration option. The first ICON can be used to simulate blocking/unblocking of the HVDC. Normally it is set as zero. At any instant of the simulation setting ICON(M) =1 will start blocking the HVDC. Blocking is simulated by reducing the DC current order at a rate given by CON(J+52). Unblocking can be simulated by setting ICON(M)=2 by increasing the DC current order at a rate given by CON(J+53). ICON(M+2) is used to select the control configuration by setting its value respectively (1, 2, or 3).

By setting ICON(M+1) = 1 and VAR(L+21) (dc current order) to any desirable value, it is possible to simulate changes in HVDC power including simulation of overload capability.

An internal integration procedure is embedded into the model that allows the use of a normal integration step for PSS®E simulation.

The PSS®E DYRE format (to be used in the dynamics input data file) for the CDC7T model is shown below:

‘DC Line Name’ 'CDC7T ' 0 0 ICON(M+2) ICON(M+3) List of CONs /

Example of a complex PSS®E simulation for a DC Line with the Long Cable is shown in Figure 2.



0sec<T<1sec – unperturbed run
T=1.0 sec – dc line fault on inverter side of pole 1
T=1.5 sec. – blocking pole 1 with the rate of 2000 A/sec.
T=5 sec. – overloading pole 2 by 50%
T=10 sec. – unblocking pole1 with the rate of 500 A/sec.
T=15 sec. – restoring the system

Figure 2 - Example of Complex Simulation for a DC Line with the Long Cable

Download document as .pdf